There has been the case that in optical transport network (OTN) transmission specified in International Telecommunication Union-Telecommunication Standardization Sector (ITU-T), multiplexing of frames is performed in order to achieve faster optical transmission. That is, there has been the case that in an optical channel data unit (ODU) frame that constitutes an optical channel transport unit (OTU) frame, lower-layer ODU frames are, in addition to a client signal, further multiplexed in a payload (see Japanese Laid-open Patent Publication No. 2012-65342). Hereinafter, such a low-layer ODU frame is described as a lower order (LO)-ODU frame in distinction from a higher order (HO)-ODU frame in which the low-layer frame is stored.
For example, when an optical receiver divides a client signal of 400 Gbps Ethernet (registered trademark) (400 GbE) into four 100-Gbps signals and transmits the signals, the above-mentioned client signal is first mapped to an LO-ODU frame of ODU4Cn (n=4) that is constituted of four lanes. Thereafter, the optical receiver maps the above-mentioned client signal to an HO-ODU frame of ODU4Cm (m=4) thus generating an OTU frame capable of high speed transmission at 400 Gbps. In the OTN transmission, signals are hierarchized and the bit rates of the respective layers differ from each other and hence, signal processing for maintenance, monitoring, or the like is usually performed for each layer.
Furthermore, the optical receiver refers to the overhead (OH) of the OTU frame that has been received to perform the signal processing for maintenance, monitoring, or the like (hereinafter, referred to as “OH processing”). Although the OH processing is achieved by a device (an application specific integrated circuit (ASIC), field programmable gate array (FPGA), or the like) in the optical receiver, the device in the optical receiver does not operate with the clock (100 GHz, for example) that follows 100 Gbps. Accordingly, the device in the optical receiver performs the OH processing with respect to the OTU frame by parallel processing to be performed with a clock on the order of 200 MHz to 400 MHz.
FIG. 7 is a view illustrating a manner that data is rearranged in advance of the OH processing of the OTU frame. As illustrated in FIG. 7, an OTU frame F100 is received and thereafter, serial-parallel conversion of the OTU frame F100 is performed (S101). However, since the OTU frame F100 is received continuously, an OH to be processed is not necessarily located on the head side of data depending on the timing of conversion. As a result, it is difficult to specify the position of the OH. Accordingly, the rearrangement (shift) of the OTU frame F100 is performed so that the OH to be processed always appears at a predetermined position (the first bit of the head part, for example) of a parallel signal (S102). After the rearrangement of the OTU frame F100, OH position specifying processing and the OH processing are performed with respect to the OTU frame F100 as a parallel signal (S103).
However, in related frame processing, rearrangement processing is separately performed for each layer and hence, there has been a drawback that the scale of a circuit is increased. Hereinafter, the explanation is specifically made with reference to FIG. 8. FIG. 8 is a view for explaining the frame processing performed for each layer in a related technique. As illustrated in FIG. 8, in the frame processing performed on the side of demapping, the above-mentioned rearrangement processing of data is performed for each layer.
In FIG. 8, an OTUCn frame F200 is a first-layer frame, and an ODU4Cn frame F300 is a second-layer frame. The OTUCn frame F200 has an OH part F210 and a forward error correction (FEC) part F220 in addition to a payload part, and the ODU4Cn frame F300 having the OH part F310 is multiplexed in the payload part. Here, each of filled portions (black portions) of the OTUCn frame F200 and the ODU4Cn frame F300 constitutes a frame alignment signal (FAS) that indicates the head position of each frame.
The serial-parallel conversion of the OTUCn frame F200 received by the optical receiver is performed in order to lower a clock rate (S201) and thereafter, the head position of the OTUCn frame F200 is detected (S202). First rearrangement processing is performed at S203. That is, in order to easily perform successive OH processing with respect to the OTUCn frame F200, the OTUCn frame F200 is rearranged so that the above-mentioned head position is located at the head part (most significant bit (MSB), for example) of parallel data. Furthermore, the OH processing with respect to the OTUCn frame F200 of the first layer is performed (S204).
In second rearrangement processing, the OH part F210 and the FEC part F220 are deleted from the OTUCn frame F200 and thereafter, in order to easily perform frame conversion processing between layers later, the OTUCn frame F200 is rearranged so that the parallel data that constitutes the payload part is formed in a rectangle shape (S205, S206). Next, the ODU4Cn frame F300 is extracted from the rearranged OTUCn frame F200.
In the same manner as S202 above, the head position of the ODU4Cn frame F300 is detected in the extracted ODU4Cn frame F300 at S207. Third rearrangement processing is performed at S208. That is, in order to easily perform successive OH processing with respect to the ODU4Cn frame F300, the ODU4Cn frame F300 is rearranged so that the above-mentioned head position is located at the head part (MSB, for example) of the parallel data. In the same manner as S204 above, the OH processing with respect to the ODU4Cn frame F300 of the second layer is performed at S209.
As mentioned above, in the related frame processing, the rearrangement processing is performed separately for each layer; that is, each of the first and second layers. The rearrangement processing is performed by a selector circuit or a control circuit and hence, the circuit scale of the optical receiver is increased along with the increase of the rearrangement processing. Particularly, in high-speed transmission at a transmission rate exceeding 100 Gbps, a parallel number of 640 or more is estimated and hence, the increase in rearrangement processing significantly influences on the circuit scale. This phenomenon becomes a factor of difficulty in frame processing by existing devices such as the FPGA.